This invention deals with the Arithmetic and Logic Unit (ALU) section of computing systems, and more particularly it deals with synchronous ALUs having a look-ahead carry chain.
Presently, one type of computing systems with ALUs use a look-ahead carry chain to improve the performance of the system, i.e. increase the speed of the computations. Very briefly, a conventional look-ahead carry chain is made up of a plurality of serial slices, with each slice having a predetermined number of input bit pairs together forming a group. Within each slice a carry bit is propagated serially from the lower input pairs to the higher input pairs. However, the carry input from one slice to the next successive slice is not taken from this slow propagating carry bit, but is instead generated from the group carry-propagate (P.sub.g) and group carry-generate (G.sub.G) signals produced in the current and all of the prior slices. That is, the carry chain is "looking ahead" for the carry information between slices by generating a series of group carry signals, thus avoiding the propagation delay of the carry bit between all of the input bit pairs. A serious problem with this type of system is that the performance of the system is still always limited by the worst case propagation delay of the look-ahead carry chain i.e. the propagation of the group carry information. For a synchronous system this means that the smallest cycle time obtainable must be at least as long as the propagation delay for the combination of input bits that produces the longest group carry ripple.
In some present day systems, the required cycle time is shortened by using a carry-save scheme. In this case, the system obtains all the intermediate (that is, bit or group) sums and carrys is one cycle, and combines them in a subsequent cycle to obtain the final answer. The problem of this approach is that the system must now pay an increased price in the hardware complexity required to implement a carry-save ALU.